Questions about physical memory protection using segments

I'm prototyping a capability based pointer scheme ala cheri, which maps poorly to paging and is better represented by se

I'm prototyping a capability based pointer scheme ala cheri, which maps poorly to paging and is better represented by segment based memory protection models. This blog post from RISCv paints an hardware mechanism that seems very well suited to my approach, having 64 segments of arbitrary size, but I was playing also with ARM designs where the number of allowed segments is only 16. Let's say I have a multicore CPU, my questions are: - Are the segments CPU wide or are they configurable for each core? - I imagine that each time the scheduler switches the thread in execution I need to reconfigure the segments, don't I? - What are the performance characteristics of reprogramming segments? Is it a cheap operation like an ALU operation, a medium operation like loading main memory, or an expensive one like lock based ops?